The present invention relates to a semiconductor integrated circuit device and more particularly to a technology suitably applied to a data processing device such as a single chip microcomputer and a single chip microprocessor that incorporate a central processing unit and a data transfer device.
A single chip microcomputer, as described in the "LSI Handbook," page 540-541, published by Ohmsha Ltd. on Nov. 30, 1984, generally consists of a central processing unit (CPU) and other functional blocks including a read only memory (ROM) for program storage, a random access memory (RAM) for data storage, and an input/output circuit for input and output of data, with all of these blocks formed on a single semiconductor substrate.
Such a single chip microcomputer, which further incorporates a direct memory access controller (DMAC) to enable data transfer independently of the CPU, is described in the "H8/3003 Hardware Manual," published in March 1993 by Hitachi, Ltd.
This DMAC is started by an interrupt request and has operation modes such as repeat mode and block transfer mode. This DMAC is suited for control of stepping motors and of printout data in a printer. In this example, data transfer for up to eight channels can be made. The data transfer by the DMAC, as it is independent of the CPU, needs to stop the CPU only in those bus cycles that are required for the DMAC data transfer, so that in bus cycles other than those required for the DMAC data transfer, the CPU can continue the data processing currently being executed.
Take, for example, a case where byte data are transferred to the input/output circuit by the above-mentioned DMAC and a transfer source address and a transfer destination address are incremented. Assuming that an access to RAM requires two states and an access to the input/output circuit requires three states, a single data transfer requires six states including one state of dead cycle used for DMAC internal operation. In this specification, one cycle of reference clock in the single chip microcomputer or a semiconductor integrated circuit device is defined to be one state.
Such a DMAC, however, has a transfer source address register, a transfer destination address register, a transfer counter register and a control register in each channel. Hence, if data transfer is made in a large number of channels, these registers need be provided for each of the channels.
The number of channels can be increased by limiting the number of bits of the address specification register.
The "H8/532 Hardware Manual," published in December 1988 by Hitachi, Ltd. describes a single chip microcomputer that incorporates a data transfer device, a so-called data transfer controller (DTC), in which the registers for holding transfer information, such as the transfer source address register, transfer destination address register, transfer counter register and control register, are arranged on a general-purpose RAM with high memory density to prevent an increase in the logic and physical size. This DTC allows data transfer to be performed by virtually any interrupt origin.